Education 4u
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13:29
D flip flop | Edge Triggered | STLD| Lec-118
Education 4u
514 views • 6 days ago
16:19
S R Flip flop | Edge triggered | Waveforms | STLD | Lec-117
Education 4u
340 views • 8 days ago
13:12
D Latch | Gated | Truth Table | STLD | Lec-116
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264 views • 9 days ago
18:58
SR latch | Gated | Truth Table | STLD | Lec-115
Education 4u
246 views • 9 days ago
16:19
S R Latch | NAND gate | STLD | Lec-114
Education 4u
798 views • 3 weeks ago
20:17
S R Latch | NOR gate | STLD | Lec-113
Education 4u
350 views • 3 weeks ago
13:03
Flip flops | Latches | STLD | Lec-112
Education 4u
294 views • 3 weeks ago
18:06
Sequential circuits | Classification | STLD | Lec-111
Education 4u
280 views • 3 weeks ago
11:01
PROM | Logic Diagram | Example problem | STLD | Lec-110
Education 4u
525 views • 1 month ago
21:47
PLA with PLA table | Example problem | STLD | Lec-109
Education 4u
275 views • 1 month ago
15:34
Design using PLA | STLD | Lec-108
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249 views • 1 month ago
22:39
PAL with PAL table | Example problem | STLD | Lec-107
Education 4u
249 views • 1 month ago
15:01
Design using PAL | STLD | Lec-106
Education 4u
230 views • 1 month ago
15:21
Programmable Array Logic | PLA, PROM | STLD | Lec-105
Education 4u
254 views • 1 month ago
14:59
ROM | Types M-ROM, P-ROM, EPROM, EEPROM | STLD | Lec-104
Education 4u
245 views • 1 month ago
20:04
ROM | Programmable Logic Device | Part-2/2 | STLD | Lec-103
Education 4u
233 views • 1 month ago
16:14
Programmable Logic Device | Part-1/2 | STLD | Lec-102
Education 4u
277 views • 1 month ago
11:01
VHDL and Verilog codes | Differences VHDL & Verilog | Digital Design | Lec-18
Education 4u
481 views • 1 month ago
16:06
Component declaration and instantiation | VHDL | Digital Design | Lec-17
Education 4u
408 views • 1 month ago
12:28
Conditional and selected signal assignment statements | VHDL | Digital Design | Lec-16
Education 4u
253 views • 1 month ago
12:27
Concurrent signal assignment statement | Concurrent Vs Sequential | VHDL | Digital Design | Lec-15
Education 4u
306 views • 1 month ago
15:07
Process statement | Case, Null , Loop | Part-2/2 | Digital IC Design | Lec-13
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389 views • 1 month ago
17:03
Process statement | Variable, Signal, Wait & If | Part-1/2 | Digital IC Design | Lec-13
Education 4u
319 views • 1 month ago
15:25
Operators in VHDL | Logical, Relational | Digital IC Design | Lec-12
Education 4u
260 views • 1 month ago
11:48
Data types | Pre-defined type & Scalar type | Part-2/2 | Digital IC Design | Lec-11
Education 4u
452 views • 1 month ago
18:35
Data types | Pre-defined type & Scalar type | Part-1/2 | Digital IC Design | Lec-10
Education 4u
404 views • 1 month ago
11:46
VHDL | Data objects | Signal & File | Part -2/2 | Digital IC Design | Lec-09
Education 4u
334 views • 1 month ago
13:21
VHDL | Data objects | Constant & Variable | Part -1/2 | Digital IC Design | Lec-08
Education 4u
303 views • 1 month ago
13:24
VHDL | Identifiers| Basic & Extended | Digital IC Design | Lec-07
Education 4u
393 views • 2 months ago
16:31
VHDL Code | Configuration and Package declaration | Digital IC Design | Lec-06
Education 4u
487 views • 2 months ago
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