State Machines - coding in Verilog with testbench and implementation on an FPGA
Visual Electric Visual Electric
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 Published On Jan 20, 2021

Finite state machines are essential tool hardware and software design, but they are actually quite simple to understand. We walk through 1) What is a finite state machine?, what is the difference between a Moore and Mealy state machine? 2) How to design a state machine, 3) How to code a machine in Verilog.


We will be using the example of a simple pair detector, but the principle can be applied for any state machine.

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